1. Field of the Invention
The present invention relates generally to an I/O compression circuit for a semiconductor memory device and, more particularly, to an I/O compression circuit that reduces the number of I/O data pins and time required for testing the memory device.
2. Description of the Background Art
In testing a semiconductor memory device, a test time is dependent upon the number of chips that can be tested at one time. The test time can be reduced by decreasing a number of I/O data pins used in the test. Therefore, a compression device that transmits data to a plurality of internal data buses through one external I/O data pin is typically employed.
In a conventional I/O compressor for a semiconductor memory device, one data signal is identically transmitted to a plurality of transmission lines through a single I/O data pin.
When performing a test that writes the same or identical data on adjacent data buses, data signals input to one I/O data pin are identically transmitted to a plurality of adjacent data buses through the compressor (i.e., the same data is transmitted via the adjacent data buses).
However, when for performing a test that writes different data on adjacent data buses, the different data are written on separate I/O data pins corresponding to the data buses, without using the compressor for the test. As a result, a large number of I/O data pins are required and the data write time and, thus, the total time for the test is increased.